1. Field of the Invention
The present invention relates to an automatic focus adjustment apparatus, and more particularly to an automatic focus adjustment apparatus which detects the deviation amount of the focal position of an optical system as the difference between the outputs of a pair of light receiving means, which performs a shifting of the optical system in response to the amount of detected focal deviation, and terminates the shifting of the optical system when the above stated signal difference is in a predetermined in-focus range.
2. Description of the Prior Art
In recent years, the automating of the operation of various photographic apparatus has advanced and various methods have been proposed relating particularly to auto-focus adjustment apparatus. FIG. 1 shows the principle of an auto-focus adjustment apparatus as known in the art, as seen from Japanese Patent specification Nos. 809/84 or 15244/85.
In FIG. 1 the symbol L0 indicates an objective for use in camera photography which is shifted along an optical axis X by a drive means such as a motor or the like. Two lenses L1 and L2 are arranged on both sides of the objective L0, behind which a light source I and a pair of photodiodes DA and DB are respectively provided. The photodiodes DA and DB are constructed to shift at roughly a right angle to the optical axis X in response to the shift moving of the objective L0.
In the above arrangement auto-focus adjustment is performed as follows.
Light from the light source I is radiated through the lens L1 at a photo-subject along the optical axis X, and the light reflected therefrom is directed through the lens L2 onto the photodiodes DA and DB. The light from the light source I is radiated at a fixed radiation angle, thus the distance from the optical axis X of the photodiodes receiving the light reflected from a photo-subject varies along an axis perpendicular to the optical axis x in dependence on the distance of the photo-subject from the optical system. Accordingly, if the movement of the objective L0 and the two photodiodes DA and DB is adjusted such that the volume of reflected light is incident in equal amounts on the two photodiodes DA and DB in the state of the properly focused objective, it is possible to perform focus adjustment automatically by checking the outputs of the photodiodes DA and DB.
Prior art active auto-focus adjustment systems as described above have the drawback that when a photo-subject is at a great distance or when a source of light disturbing the light signal from the light source I is in the front of the camera, the signal to noise ratio in the reflected light detected by the photodiodes becomes poor and normal focus adjustment cannot be performed.
When the signal to noise ratio is degraded, despite the camera being in a focused condition and the position of the camera and the photo-subject not changing, there are cases in which the objective will shift due to disturbing light, and unseemly problems will occur such as the obscuring of focus, and changes in image size.
In view of the above problems, improved prior art auto-focus adjustment apparatus have been advanced which can reliably perform auto-focus adjustments even in the presence of the disturbing light.
An explanation of such an example of prior art will be given below with reference to FIG. 2. In the arrangement to be explained below, the gearing system of the camera objective and the photodiodes DA and DB for detecting reflected light will be considered to be of a configuration similar to that of the prior art shown in FIG. 1.
FIG. 2 shows a circuit diagram of an auto-focus adjustment apparatus in which symbols DA and DB indicate adjacently arranged photodiodes used for detecting reflected light. The output of the photodiodes DA and DB are amplified by amplifiers 1A and 1B, and then sent to filters 2A and 2B, respectively.
A light source I is driven at an oscillation frequency of a reference oscillator 13 via a radiance control element 14 equipped with a driver. In order to prevent the disturbance of the incident light, the frequency chosen preferably differs from the frequencies of commercial use power supplies used for indoor lighting systems.
Accordingly, filters 2A and 2B are provided so that only signals in the range of the light emitted from the light source I are allowed to pass through. The output of the filters 2A and 2B are input via electrically operated switches 3A and 3B to integrators 4A and 4B.
Output voltage VA of the integrator 4A is input to the non-inverting input terminals of comparators 5AH and 5AL. Output voltage VB of the integrator 4B is input to the non-inverting input terminals of comparators 5BH and 5BL.
Power supply voltage divided by serially connected resistors R1-R3 is supplied in threshold voltages through connection points A and B to the inverting input terminals of each of the comparators. A voltage VH at the connection point of the resistors R1 and R2 is supplied to the comparators 5AH and 5BH as threshold voltage.
A voltage VL of the connection point of the resistors R2 and R3 is supplied to the comparators 5AL and 5BL. These voltages VH and VL are determined in accordance to the degree of focusing precision required.
The output of the comparators 5AH and 5BH are connected to the input of an OR-gate 61. The output of the OR-gate 61 is input to an inverter 71, a delay circuit DL1 comprising a mono-multi vibrator and the like, the trigger terminals of D flip-flops 91 and 92, and a connection point C of a block 20. When one or the other of the comparators 5AH or 5BH becomes high level, a high level pulse is output, and the D flip-flops 91 and 92 are triggered by this pulse.
The outputs of the comparators 5AL and 5BL are applied to the data inputs of the respective D flip-flops 91 and 92. The non-inverting output of the D flip-flop 91 and the inverting output of the D flip-flop 92 are input to AND-gate 82, and the inverting output of the D flip-flop 91 is input to the AND-gate 83. The third input terminal of the AND-gate 82 and the other input terminal of the AND-gate 83 are connected through resistors R4 and R5, respectively, to power supply voltage, and the electrical potentials of both of these input terminals are controlled by switches 3C and 3D which are normally open. The switches 3C and 3D are provided respectively on both edges of the travel range of the objective, and when the objective shifts to the infinity mark or to the maximum close range position, the switches 3C and 3D suppress the AND-gates 82 and 83, whereupon the movement of the objective by the motor 11 is terminated.
A motor controlling circuit 10 bi-directionally drives the motor 11 which moves the objective in response to the output of the AND-gates 82 and 83. The motor 11 is pre-coordinated to move in accordance to the amount of light incident on the photo-diodes DA and DB in the direction which will equalize the above-mentioned amounts. The connection point C of the block 20 is connected to one input of an OR-gate 63, and the output of the OR-gate 63 is connected to the reset terminal of a counter 12. The clock input of this counter 12 is connected through a connection point E to the above stated reference oscillator 13, and advances with the fall of the clock pulse of the reference oscillator 13. At the same time, the clock pulse output of the reference oscillator 13 is connected through the connection point E to the other input terminal of an AND-gate 84. The output of this AND-gate 84 is connected to the remaining input of the OR-gate 63. An output Qn of the counter 12 is connected to the top input of the AND-gate 84.
The output Qn of the counter 12 resets the D flip-flops 91 and 92 via the connection point D, and is concurrently connected to the top input of the OR-gate 62. The output of the OR-gate 62 resets the integrators 4A and 4B, and the output of the inverter 71 works to open the switches 3A and 3B.
Next, a detailed explanation of the operation of the above described arrangement will be given below.
The photodiodes DA and DB produce signals depending on the amount of light received, and only the radiation frequency component of the light source I of these output signals is extracted by the filters 2A and 2B, respectively, and sent through the normally closed switches 3A and 3B to the integrators 4A and 4B. The output voltages of each of the integrators are described, as shown in FIG. 3, in accordance to the amount of light received after the commencement of measuring.
A case will be described below in which the output voltages of the integrators 4A and 4B are increased over time in a manner indicated by the reference symbols VA and VB'.
The amount of light incident on the side of the photodiode DA is greater, thus at a time T the integrated voltage VA reaches the threshold value VH of the comparator 5AH. Accordingly, the comparator 5AH inverts, and a high level is output from the OR-gate 61, whereupon the D flip-flops 91 and 92 are triggered. At this time, the data input of the D flip-flop 91 is high level because, as may be seen in FIG. 3, the voltage VA has already exceeded the threshold value VL of the comparator 5AL. Further, the data input of the D flip-flop 92 is low level because the voltage VB', at this point, has not yet reached the voltage VL.
Accordingly, the D flip-flop 91 and the D flip-flop 92 produce high and low level signals, respectively, due to the triggering of each flip-flop. Needless to say, since the respective inverting outputs produce voltages opposite thereto, the inputs of the AND-gate 82 are all high level and the inputs of the AND-gate 83 become high level and low level. Therefore, the AND-gate 82 produces a high level signal, and the AND-gate 83 a low level signal.
Accordingly, the motor controlling circuit 10 drives the motor 11 and shifts the objective and the photodiodes such that the amount of light received by the photodiode DB increases. In the event that the balance of the amounts of received light is reversed, the objective is shifted in the direction opposite that stated above by an exactly similar operation.
Simultanuously with the triggering of the D flip-flops 91 and 92, the integrators 4A and 4B are cut off via the inverter 71, and reset to their initial values by means of the OR-gate 62 following the elapse of a time delay established by the delay circuit DL1. The counter 12 inside the block 20 is also reset via the OR-gate 63.
This counter 12 establishes the maximum period of integration, and after the counter 12 is reset at the end of a measuring period in the above stated manner, if during a next operation the counter 12 has not been reset by the time it has counted a fixed number of clock pulses of the reference oscillator 13, it will be determined that a sufficient amount of measured light could not be received, whereupon the counter 12 generates a short pulse to reset the D flip-flops 91 and 92 and the integrators 4A and 4B. Simultaneously, the counter 12 resets its own count value via the AND-gate 84 in synchronization with the clock pulse.
In the event that the respective integrator values increase in a manner indicated by the symbols VA and VB, when the voltage VA has reached the voltage VH, the comparators 5AL and 5BL have already inverted in concert, thus the outputs of the D flip-flops 91 and 92 become high level together. Accordingly, the AND-gates 82 and 83 are isolated concurrently, whereupon the motor 11 is suspended and the movement of the objective is restrained. When one or the other of the output integration values of the photodiodes DA and DB reaches the voltage VH, in the event that the other output value is the same or higher than the voltage VL, it means that an in-focus condition has been established.
FIG. 4 shows another embodiment of the prior art in which the block 20 in FIG. 2 is replaced by a block 21, and the non-inverting input of the comparator 6H is connected to the connection point of a resistor R6 and a capacitor C1. The collector of a transistor Tr1 is also connected to this connection point. The other end of the resistor R6 is connected to power supply voltage, and the other end of the capacitor C1 is connected to ground.
The connection point of resistors R7 and R8 which divide power supply voltage are connected to the inverting input of a comparator 6H. The output of the comparator 6H is connected to the reset input of a RS flip-flop 93. The point C is connected to the left and top inputs of OR-gates 64 and 65, respectively. The output of the OR-gate 65 is connected to the set input of the RS flip-flop 93. The output of the OR-gate 64 is connected through a resistor R9 to the base of the transistor Tr1. The emitter of the transistor Tr1 is connected to ground.
The inverting output of the RS flip-flop 93 is connected to the one input of the OR-gate 64 and to a point D, and concurrently through a delay circuit DL2 to the other input of the OR-gate 65.
Next, an explanation will be given below of the operation of the arrangement of FIG. 4.
When one or the other of the outputs VA and VB of the integrators 4A and 4B reach the voltage VH, a positive pulse appearing at the point C, in a manner similar to the apparatus of prior art described above, causes the transistor Tr1 to be turned ON via the OR-gate 64 and the resistor R9, and discharges the capacitor C1. Simultaneously, the pulse sets the RS flip-flop 93 via the OR-gate 65.
The capacitor C1 commences charging via the resistor R6 when the pulse from the point C disappears.
The electrical potential of the capacitor C1 is compared to the electrical potential of the connection point of the resistors R7 and R8 by the comparator 6H, and when the electrical potential of the capacitor C1 exceeds the electrical potential of the connection point, the comparator 6H produces a high level signal, and resets the RS flip-flop 93.
The inverting output of the RS flip-flop 93 produces a high level signal and resets via the point D the D flip-flops 91 and 92, and the integrators 4A and 4B, and concurrently causes the transistor Tr1 to be turned ON via the OR-gate 64 and the resistor R9, whereupon the capacitor C1 discharges. Further, the inverting output of the RS flip-flop 93 resets itself via the delay circuit DL2 and the OR-gate 65.
At this time, the delay circuits DL1 and DL2 establish a time delay sufficient for discharging the capacitor.
Accordingly, the maximum period of integration is set according to the time constant of the resistor R6 and the capacitor C1 and the voltage division ratio of the resistors R7 and R8.
Prior to the elapse of the maximum period of integration, in the event of the outputs VA or VB of the integrators 4A and 4B reach the reference electrical potential VH, a positive pulse appears at the point C which turns on the transistor Tr1 via the OR-gate 64 and the resistor R9, whereupon the capacitor C1 discharges, and then subsequently recommences charging. Accordingly a mono-stable multi-vibrator-like function with a re-triggering capability is realized. In this manner, a maximum integration period is established, afresh.
In the above two embodiments in the prior art the performance of auto-focus adjustment is possible even in the event that there is a certain level of the disturbing light or a photo-subject is comparatively far away. However, with video cameras of recent make there is a trend toward the attachment of high magnification zoom lenses, in which case there is a need for auto-focus adjustment systems which can perform range finding to great distances.
The problem in such cases lies in the deterioration of the signal to noise ratio of the light signal received. The principal reason for this is the attenuation of reflected light when the photo-subject is at a great distance or the reflexibility of a photo-subject is poor.
When the signal to noise ratio deteriorates, the below described phenomena occur.
We shall assume ideal conditions of no noise and consider the above stated output integration values VA and VB of the integrators to be in a condition denoted by VA and VB of FIG. 5. In this case an in-focus condition is ascertained and the motor 11 used for shifting the objective is suspended. If the positional relationship of the photo-subject and the camera does not change, the integration values VA and VB maintain the condition of FIG. 5. However, in reality, noise does exist, thus there are instances in which VB which is based on the received light signal changes to VB' or VB" (actually, integration time also changes, but for the present this is ignored).
In the event that an integration voltage such as VB' is obtained, as before, an in-focus condition is ascertained and the motor remains suspended. In the event of VB", when VA reaches the reference voltage VH, an out-of-focus condition is adjudged and the motor is driven because VB" has not reached the reference voltage VL. As a result, when the signal to noise ratio of the signal component deteriorates, the so-called apparent dead zone narrows. If the signal to noise ratio deteriorates further, the apparent dead zone disappears, and hunting starts.
A method which increases the radiance of the light source sending the light signal is conceivable as a countermeasure to improve the signal to noise ratio, however recent years have seen a trend toward low power consumption electrical equipment thus making implementation of the concept problematic.